September 12th, 2014
Alireza Ejlali, Ph.D, Associate Professor
Director of laboratory
ejlali AT sharif.edu
Current Ph.D. Students
bazzaz AT ce.sharif.edu
Thesis Memory Management and Architecture in Embedded Systems for Energy Efficiency
Abstract Today, memories are responsible for a considerable portion of energy consumption in embedded systems, mainly because of their static leakage power consumption. Memories used in embedded systems are usually based on either SRAM (mostly used on-chip as cache or scratchpad memory) or DRAM (mostly used off-chip as main memory). The high leakage power of these memories (especially SRAM) can not be ignored which has persuaded researchers to find alternative solutions. In recent years, non-volatile memories have attracted researcher's attention because their leakage power is much lower as compared to conventional memories like SRAM. The two most promising alternatives are PCM and STT-RAM. In this project, we propose new solutions for reducing the energy consumption of embedded systems by improving the memory architecture and/or using non-volatile memories. Furthermore, we study the effect of limited endurance of these memories on embedded systems and how their other characteristics such as slower write operation can affect systems with real-time constraints.
Mohammad Taghi Teimoori
teimoori AT ce.sharif.edu
Thesis Exploiting Approximate Memories in Embedded Systems
Abstract Approximate computing (AC) is a promising paradigm in low power design and high performance design for computing systems especially for embedded systems. Most of the previous studies in AC have focused on arithmetic and logic unit. However, memories are a main contributors to system energy consumption and performance. In this project, we investigate techniques to improve the energy consumption and performance of embedded systems by exploiting approximate volatile and non-volatile memories.
Mostafa Jafari Nodoushan
Jafarin AT ce.sharif.edu
Thesis System Level Thermal Management for Real-time Embedded Systems
Abstract The continuous increase of chip complexity with shrinking feature sizes, has led to more power density in modern processors. This subject has posed tremendous challenges on removing the generated heat from the chip and prevent it from overheating. High temperature directly affects the chip reliability and lifetime which are crucial in safety-critical embedded systems. It has been shown that a 10ºc reduction of peak temperature cab double the lifetime of the chip. However the use of fan and expensive advanced packaging techniques is not common in these systems and so the amount of heat that can be removed from the chip is limited. The main purpose of this research is to propose novel system level temperature management techniques to control temperature within an admissible range while considering other systems criteria like tasks deadlines.
rnarimani AT ce.sharif.edu
Thesis Thermal-aware power/energy optimization in heterogeneous multi-core embedded systems, Approximate computing
Abstract Recent embedded systems adopt high performance processors to support various applications. As an important side effect, higher performance inevitably leads to power density increase, eventually resulting in thermal problems. An approach to reduce embedded system's temperature is approximate computing. For example in real-time task scheduling, tasks can be divided into different versions(low quality versions and high quality versions). low quality tasks can be used to meet thermal constraint and high quality tasks can be used to meet performance constraint
mansari AT ce.sharif.edu
Thesis System-Level Power Management in Fault-Tolerant Embedded Systems
Abstract Multicore platforms provide great opportunity for implementation of fault-tolerance techniques to achieve high reliability in real-time embedded systems. In spite of the huge potential for fault-tolerant techniques in multicore platforms, due to the Thermal Design Power (TDP) constraint, designers of fault-tolerant embedded systems face a challenge in deciding how to use them. TDP is considered as the highest sustainable power that a chip can dissipate without triggering any performance throttling mechanisms, e.g. Dynamic Thermal Management (DTM). If a chip temperature violates its TDP, it automatically restarts or significantly reduces its efficiency to prevent permanent damage. The continually increase in the degree of integration along with using fault-tolerant techniques can increase power consumption and rise the peak power which can lead to violate the TDP constraint. In this research, we aim at considering effects of fault-tolerant techniques on the power consumption in real-time embedded systems.
bsafaei AT ce.sharif.edu
Thesis Low Power and Reliable Routing Protocol for Internet of Things
Abstract Internet of Things (IoT) is a system comprising a communicative infrastructure which connects an enormous amount of identified, low-power embedded devices through exploitation of Internet and communication technologies without human intervention. The potential applications of IoT are ample, starting from smart homes to smart cities. In this context, the Low Power and Lossy Networks (LLNs) play an essential role to underpin the deployment infrastructure for IoT. Thus, the different international standardization bodies such as IETF, IEEE, 3GPP standardized new protocols to meet the requirements and emerging applications of IoT. Data transmission in harsh environments via dynamic and lossy wireless links is inherently unreliable, leading to excessive retransmissions, large amount of energy consumption and long occupation time of the shared wired and wireless medium. Therefore, reliable and energy-efficient data delivery has to be considered as two important aspects of IoT applications. Hence, routing is of paramount importance for LLNs, as data has to be relayed via tremendous number of resource constraint embedded devices. The pervasiveness of LLNs in IoT applications calls for effective routing solutions to provide ubiquitous connectivity for tremendous number of low-cost and low-power embedded devices. Existing LLNs routing protocols can be categorized into: reactive (on-demand) routing, proactive routing and geographic routing. Our goal is to consider the resource constraints and dynamic attributes of the wireless environment and to research towards finding a more energy-efficient, reliable, stable, and scalable routing in IoTs.
mohammad_salehi AT ce.sharif.edu
Thesis System-Level Techniques for Low-energy Fault-tolerance in Hard Real-Time Embedded Systems
Abstract Many embedded systems which are employed in safety-critical applications: i) must be highly reliable, ii) are severely energy-constrained, and iii) have hard real-time constraints. To satisfy the timing constraints, fault-tolerance capability is usually achieved through hardware redundancy. For such applications the use of other methods may has limited utility. Although it seems at a first glance that hardware redundancy can incur high energy overheads, its use can decrease the response time and create more slack times. The main purpose of this project is to provide new system-level techniques to manage the slack times for achieving low energy consumption while considering fault tolerance and real-time capabilities as the main characteristics of many embedded systems.
mohajjel AT ce.sharif.edu
Thesis Reducing worst case execution time of tasks in multicore real-time embedded systems by scratchpad memory management
Abstract Multicore processors are increasingly used in the design of real-time embedded systems. While some multicore processors use cache memory to reduce average execution time, as in real-time applications usually worst-case execution time (WCET) is more important, many real-time embedded systems use scratch-pad memory (SPM) instead of cache. Unlike cache, SPM is a software-controlled memory and its content is visible to software. Therefore, in contrast to cache, software programmer (or compiler) can fully control the content of SPM to achieve predictability required for analyzing and reducing WCET. However, the cost of this predictability is a burden on the software to manage SPM. SPM management (allocating SPM space to system tasks) can be especially more complex when SPM is shared among the cores. Indeed, as resource sharing is one of the remarkable features of multicore processors, all or part of on-chip memory (cache or SPM) is usually shared among the cores. In this research, we intend to study shared SPM management in multicore real-time embedded system with the aim of reducing WCET.
Current M.Sc. Students
Thesis Energy Efficient Scheduling in Mixed-Criticality Embedded Systems
Abstract Due to the continuing progress in CMOS technology and increased number of cores within a chip, multiple components with different levels of criticality have been integrated into a common hardware platform. These systems with these characteristics are known as Mixed-Criticality Systems (MCS). Also, due to the migration towards multi-core systems, power consumption and specifically instantaneous power consumption is the main concern. To avoid the use of cooling technology, we need to reduce the instantaneous power consumption of the system. However, most existing approaches in MCS have paid attention to reliability guaranteed and energy minimization. Therefore, we consider a dynamic scheduling algorithm based on the EDF-VD scheduling for mixed-criticality task sets that prevents concurrent execution of tasks assigned to the different cores specifically in the critical mode. To achieve this, we use service degradation for low criticality tasks in the high criticality mode. In other words, we calculate power consumption of the system at any point in time and when the total power consumption exceeds the maximum power constraint value, we suspend at least one low criticality tasks to reduce the instantaneous power consumption.
takami AT ce.sharif.edu
Thesis A Low Energy Data Allocation on Hybrid Racetrack-SRAM on-chip Memory for Real-Time Embedded Systems
Abstract Embedded systems are usually real-time and have a tight energy budget. Since the on-chip cache is responsible for 25%-50% of the processor’s area and energy consumption, Scratch Pad Memory (SPM), which is a software-controlled on-chip memory, has been widely adopted in many embedded systems due to its smaller area, lower power consumption, and better time predictability. However, with increasing the number of CMOS transistors along with density, leakage power consumption is becoming a critical issue for memory components. So, it is necessary to take advantage of the low leakage power and high density of emerging non-volatile memories. Racetrack memory is a promising non-volatile technology with high density, ultra-low leakage power, and comparable access time/energy to SRAM. In this paper, we propose a hybrid on-chip memory architecture consisting of SRAM and Racetrack memory which improves both energy consumption and performance of the system. In order to minimize the energy consumption, most of the proposed hybrid on-chip memory’s area is dedicated to racetrack memory, but considering that racetrack memory has shift and write energy/time overhead problems, we use a small SRAM alongside with the racetrack memory to reduce write energy/time overhead and decrease shift operations. Furthermore, we present a new data mapping algorithm for our architecture which helps to determine the best memory for application data considering the timing constraint of the system.
shekarisaz AT ce.sharif.edu
Thesis SPM Allocation to Tasks for Energy Saving in Multicore Embedded Systems
Abstract Energy consumption is a critical issue in embedded multicore systems due to available energy budget. Memory subsystem is one of the main components with significant role in this issue. Scratch-pad memories (SPM) provide a large potential for energy saving in on-chip memory subsystems. According to limited size of SPM, an optimal memory partitioning among tasks, can reduce energy consumption and execution time of application. In addition, emerging Non-Volatile memories (e.g. STT-MRAM, PCM, …) that have appropriate features like high density and low leakage power against SRAM, can be very helpful in reducing energy. In our research, we propose an algorithm for tasks’ scheduling/mapping and SPM allocation in order to reduce energy consumption. Also we intend to exploit Non-Volatile memories advantages over SRAM by using hybrid SPM formed by both SRAM and Non-Volatile memories.
toutounchian AT ce.sharif.edu
Thesis Power Management in Embedded Systems with Hard and Soft Real-time Tasks
Abstract Modern embedded applications such as multimedia ones have tasks with different types of timing constraints (e.g. Hard real-time, Soft real-time) in the same platform. Hard real-time tasks have to meet their deadlines in all scenarios to avoid severe consequences. However, deadline missing in soft real-time tasks does not cause serious damage. On the other hand, most of the embedded systems are fan-less and have limited energy budget. Therefore, power management for these systems is important. In this project, we proposed system-level power management techniques for embedded systems with hard and soft real-time tasks. Power management techniques must guarantee that hard real-time tasks meet their deadlines and attempt to increase the utility of soft real-time tasks.
hoseinghorban AT ce.sharif.edu
Thesis Management of interleaved memory blocks in real-time embedded system to reduce WCET and energy consumption
Abstract In embedded systems, memory blocks mostly used as scratchpad memories (SPM) to achieve more predictability. Partition memory to multiple banks and access them in parallel, increase performance of systems. Although this structure increase average case execution time (ACET) of systems but worst case execution time (WCET) is more important parameter in real-time systems. In this research we aim to analyze effects of memory interleaving on real-time systems and proposed compiler level SPM Space allocation to reduce WCET and energy consumption.
ayeganeh AT ce.sharif.edu
Thesis Peak-Power-Aware Task Replication to Manage Reliability for Multicore Embedded Systems
Abstract The number and diversity of cores in embedded systems is increasing rapidly. Modern embedded processors provide multiple cores for parallel computing, and hence power dissipation and thermal issues have assumed increasing significance in embedded system design. Meanwhile, reliability has become important concern in the design of embedded systems. Task replication is a powerful way to achieve high reliability, however, it is not possible to increase replications rapidly due to the Thermal Design Power (TDP) constraint. Exceeding the TDP constraint may active the Dynamic Thermal Management (DTM) to ensure thermal stability, but significant performance losses in frequent triggers of DTM. We consider the problem of achieving a given reliability target for a set of periodic real-time tasks running on a multicore system according to the TDP constraint.
fbahrami AT ce.sharif.edu
Thesis Exploiting non-volatile memories for soft real-time embedded systems to achieve low energy consumption
Abstract Energy consumption minimization is one of the most important goals in designing embedded systems. The memory subsystem is a major contributor to energy consumption in these systems. Non-volatile memories possess several characteristics beneficial to memory design such as non-volatility, leading to near-zero leakage energy and high density. Therefore, nowadays, use of non-volatile memories such as phase-change memory (PCM) in embedded systems is considered. On the other hand, there are two major challenges in using non-volatile memories for these systems, namely, their longer write latency and higher write energy. The goal of this ongoing project is reducing the energy and the latency costs of write operations of this memories to be suitable for soft real time embedded systems.
faezeborhani AT ce.sharif.edu
Thesis Data allocation for scratch-pad memory on embedded multi-core systems to achieve predictability and to reduce WCET
Abstract One of the main features of platforms used in embedded systems is predictability. Therefore, in many embedded systems scratchpad memory is used instead of cache because its behavior is predictable unlike cache. On the other hand, recently there has been a considerable increase in the use of multi-core systems in implementation of embedded systems. In these systems there are often shared and private caches which can be replaced with scratchpad memory in order to achieve predictable behavior needed by embedded systems. When using scratch memory in multi-core systems, sometimes it's called limited local memory. One of the concerns when using scratch memory is allocation method in memory cells. Another problem when using these systems is that in many cases the need to reduce the mean of execution time (Cache performance on area is very successful.) is secondary to the need to reduce the worst-case execution time. The goal of this project is to compare existing methods of allocating scratchpad memory cells in terms of predictability and the worst-case run time. Then a method is presented which reduces the worst-case runtime while maintaining predictability. It should be noted that another issue that must be considered here is the coherence issue of contents of the scratchpad memory.
Farimah Ramezan Pour Safaei
poursafaei AT ce.sharif.edu
Thesis Energy Efficient Dynamic Memory Allocation in Embedded Systems Equipped with Non-Volatile Memory
Abstract Since many embedded systems have a tight energy budget, it is imperative to employ energy management techniques in these systems. Moreover, due to the reactive nature of many embedded systems, they spend much of their time without any activity while they are ON; this situation underlines the importance of the memory leakage power, as memory is one of the major energy contributors in the system. Non-Volatile Memory (NVM) is very promising in solving many of these energy related issues, since they offer features including low leakage power and high density. However, NVMs have some drawbacks: more timing and energy overhead of the write operation and limited number of writes. So, exploiting NVM requires some changes in the way of managing memory. In this research we aim at evaluating the dynamic memory allocation methods in embedded systems equipped with NVM with respect to the energy consumption.
ssafari AT ce.sharif.edu
Thesis Exploiting the intrinsic redundancy of multicore platforms to achieve low-power fault-tolerance in embedded applications
Abstract Low energy consumption and fault tolerance are two major objectives in designing safety-critical real-time embedded systems. These systems need to guarantee a certain reliability level which can be achieved by using fault tolerant techniques. On the other hand, the power and energy consumption constraints are obvious characteristics of most of the embedded systems, since these systems often operate in harsh environment and may have a limited energy budget (e.g. battery). In addition, multicore platforms have emerged to be popular and powerful computing engines for many recent embedded systems. While such architectures have been employed for embedded applications that require high performance computing, they also offer new considerable opportunities for designing embedded systems where hard real-time operation, high reliability, and low energy consumption are required. Multicore platforms have an inherent redundancy which provides facilities to implement various redundancy-based fault tolerant techniques such as N Modular Redundancy (NMR) and Duplication With Comparison (DWC). In this research, we aim at using hardware redundancy in multicore platforms to achieve fault tolerance, considering the power and energy constraints in hard real-time embedded systems.
taherin AT ce.sharif.edu
Thesis Energy Management in Mixed-Criticality Fault-Tolerant Systems
Abstract Due to consideration of cost, energy efficiency, area, weight etc., there is an increasing trend in designing embedded systems to integrate different functionalities with varying criticalities (i.e. importance) into a shared computing platform. Therefore, mixed-criticality systems are typically safety-critical. Mixed-criticality systems are the next generation of complex embedded systems since mixed-criticality is known as a core foundational concept in fields such as Cyber-Physical Systems (CPS) and Internet of Things (IoT). Integrating vast amount of functionalities within mixed-criticality systems requires enormous power supplies and cause thermal problems. Therefore designing energy efficient mixed-criticality systems is vital considering often battery operated and fan-less nature of these systems. In this research, we intend to propose system-level methods for designing energy efficient fault-tolerant mixed-criticality embedded systems.
navaez AT ce.sharif.edu
Thesis Wear-leveling for NVM in real-time embedded systems
Abstract One of the most important issues in reactive embedded systems is static energy consumption due to memory unit. Non-Volatile Memories (NVMs), such as Phase Change Memory (PCM), Spin-Transfer Torque RAM (STT-RAM) have many appealing characteristics for embedded systems, such as low-cost, high density, and ultralow leakage power. The main drawbacks of NVM include high latency and power consumption for write operations, and limited write endurance. Wear-leveling techniques are necessary to help even out the write operations over the NVM chip, in order to improve its write endurance and prolong its lifetime. The goal of this study is investigating the available approach of memory allocation in real-time embedded systems equipped with non-volatile memory regarding of the impact on system lifetime, and presenting a new approach for increasing memory lifetime in real-time embedded systems.
valikhani AT ce.sharif.edu
Thesis Improving System-Level Thermal Management for Multi-Core Embedded Processors
Abstract Today, heat management is among the most significant challenges in multicore embedded systems. This is an important issue because most of these systems are fan-less and commonly used in harsh environmental conditions that could aggravate heat problem. Increased temperature itself increases static power consumption of the system which is a constraint in most embedded systems. The goal of this project is to analyze heat management methods in embedded systems. Also novel method could be proposed for embedded systems. Moreover, considering heat managements’ effect on other designing goals, e.g. real-time, is among the most important aspects of this project.
ahmadian AT ce.sharif.edu
Thesis Development of an Energy Management Technique for AutomataBased Embedded Systems
Abstract Many embedded systems have a reactive nature which means that at any time instance the system is in a state waiting for an input event. Once an input event arrives, based on this event and the present state, the system executes a task to generate an output event (usually called reaction) and then goes to the next state. On the other hand, embedded systems are widely used in safetycritical applications where system reliability is the main concern. Therefore, we focus on the use of reactive embedded systems in safetycritical applications. It has been observed that automatabased models can be effectively exploited to model applications in reactive embedded systems. Energy efficiency is one of the main design constraints of embedded systems. DVFS and DPM are common energy management techniques used in embedded systems. As mentioned reactive systems are used in safetycritical applications where fault tolerance problem is critical. In addition embedded systems are exposing to two common types of faults namely permanent faults and transient faults. Thus applying a combination of energy management and fault tolerance techniques on such systems is a must. In this project we focus on automatabased embedded systems and indicate how safetycritical reactive applications can be modeled by automata. Next we propose a reliability aware energy management technique to be applied on them.
miralaei AT ce.sharif.edu
Thesis Energy Management Technique with the Consideration of Time-Utility Functions for Soft Real-Time Embedded Systems
Abstract One of the common ways of modeling time constraint in real-time systems is time-utility function. In this case, the design aim is maximizing the value for this function. Another important fact about the real-time systems is that most of them use batteries or other portable energy generators. Therefore, there are major limitations in case of their energy consumption. A good amount of research has been done to reduce the consuming energy in hard real-time systems in comparison to the lack of work for soft real-time systems. One of the reasons could be that the deadline are specified in hard real-time systems. In reverse, the time constraint for soft real-time systems is not defined by a particular accurate number, and they are modeled with time-utility functions. Despite the sensitivity of hard real-time systems, working with soft real-time systems is more difficult because of no specific deadline or due to the limitations of modeled time-utility function. The goal of this project is to use energy management methods at system level for soft real-time systems, which use time-utility function for the tasks.
Farzaneh S. Minapour
salehiminapour AT ce.sharif.edu
Thesis Energy efficient memory management techniques for multicore embedded systems
Abstract Embedded computer systems has been significantly involved in many real-life situation. Nowadays, memories, especially SRAM, are one of the main resources of high leakage power consumption in embedded systems. The various nonvolatile memories (NVM) developed recently such as PCM, STT-RAM and MRAM provided us with a new way of addressing the memory leakage power consumption problem. My research study focuses on reducing the power consumption of multicore embedded systems by improving the memory architecture using scratch pad memories as alternatives for caches and nonvolatile memories.
Mohammad K. Taram
taram AT ce.sharif.edu
Thesis Instruction Level Energy Optimization Techniques through Compiler Assisted Architecture for Embedded Processors
Abstract Instruction level techniques have been used for fault tolerant design and power estimation. Moreover, compiler can undertake some tasks of hardware such as static scheduling and local memory management. Recently, energy and power efficiency has become a hot topic among embedded system researchers. Main advantages of compiler assisted techniques are more control & predictability and hardware size reduction, which can be utilized to gain more power reduction. Through this project, we are going to empower compiler, by modifying the architecture. Our major objectives are general energy optimization and reducing energy overhead of instruction level fault tolerant techniques.
tahmasivand AT ce.sharif.edu
Thesis Analyzing the Energy Overhead of Existing Real-Time Embedded Operating Systems
Abstract Real-time operating systems (RTOSs) have been widely used in the design of nowadays embedded systems; however we discuss in this thesis that RTOSs can impose considerable energy and time overhead. In this thesis, we analyze the impact of three existing and commonly used RTOSs (µC-OS II, Keil-OS, Emb-OS) on the energy consumption and real-time behavior of embedded systems. We have chosen these RTOSs because of their use in deeply embedded systems that are the dominant application of embedded systems. For this analysis, we have used a hardware-platform which is designed for embedded applications and is equipped with energy and power measurement circuitry. Our analysis provides useful information that can be exploited by embedded system designers to select proper RTOS for their applications. Furthermore, this thesis provides information that can be used as a guide to design more effective operating systems for embedded applications. For example, our study shows that the RTOS tick-time has a considerable impact on the system energy consumption and hence must be carefully adjusted in energy-constrained embedded systems.
karimifaatemi AT ce.sharif.edu
Thesis Design and Implementation of Software-Managed Energy Optimization Techniques for a Multi-Core Embedded Processor
Abstract Some of the energy efficiency methods in embedded systems are software based. In those, hardware remains unchanged, and software source code is manipulated into energy efficiency. Advantages to these methods include not needing hardware redundancies, implementation feasibility in COTS systems, easy implementation using compilers (or OS), and lower costs. However, some of these methods require some hardware capabilities; such as methods that set frequency and voltage requiring a controllable DC to DC convertor. Nowadays, many of the embedded CPUs in market support these features (such as StrongARM and Intel Speed Scale). For instance some of the methods are, changing processor cores’ voltage level, decreasing total number of memory access, changing memory configuration, and changing task’s scheduling. The purpose of our thesis is to perform a full comparison and evaluation of those developed methods and their combinations in various application of embedded systems and to develop new ones.
malekpour AT ce.sharif.edu
fakhraei.m AT gmail.com
abbass.rahmany AT gmail.com
khatir AT ce.sharif.edu
sharifahmadian AT alum.sharif.edu
rohbani AT ce.sharif.edu
Mohammadreza Yousefizadeh Naiini
yousefizadeh AT ce.sharif.edu
staheri AT ce.sharif.edu
amohammadi AT ce.sharif.edu
samie AT ce.sharif.edu
Mohammad Khavari Tavana
tavana AT ce.sharif.edu
tajik AT ce.sharif.edu
jalali AT alum.sharif.edu
skhodadoustan AT alum.sharif.edu
mehrtash.manoochehri AT usc.edu
Seyyed Rezgar Poorahmadi
Mohammad Hossein Shekarian